1. Field of the Invention
The present invention relates to stacked wafer structure and method of fabricating thereof, and more particularly, to a stacked wafer structure having a trough silicon via penetrate either a CIS wafer or a ISP wafer to electrically connect the device in the CIS wafer to the device in the ISP wafer.
2. Description of the Prior Art
General image sensors are roughly classified into charge coupled device (CCD) image sensors and CMOS image sensors (CISs). Compared with the CCD image sensors, the CISs are widely used in portable apparatuses.
A pixel array of a CIS includes a plurality of pixels, and each of the pixels may generate an image signal from an optical signal. In detail, each of the pixels integrates photocharges corresponding to the amount of light incident using a photodiode and generates an analog pixel signal corresponding to the integrated photocharges.
In general, the analog pixel signal output from each of the pixels is converted into a digital signal and then the digital signal is image-processed by an image signal processor (ISP).
In a conventional fabricating process, the CIS circuits and ISP circuits are formed on the same substrate, however, results in an increase in the number of processes and high cost. For example, a backside-illuminated (BIS) process is often applied to the entire substrate to thin the substrate and fabricate color filers on the back side of the substrate corresponding to the CIS circuits. During the BIS process, the substrate with the ISP circuits has no alternative but to undergo the BIS process, which will increase the fabricating time. Moreover, the line width of the ISP circuits will be compromised because the CIS circuits and the ISP circuits are fabricated by the same lithographic process, which may cause degradation in the characteristics of the ISP device.